
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
Edición de la obra RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
| Autor | Stuart Sutherland |
|---|---|
| Editorial | Sutherland HDL, Createspace Independent Publishing Platform, CreateSpace Independent Publishing Platform |
| Fecha de publicación | 2017 |
| Páginas | 488 |
| ISBN-13 | 9781546776345 |
| Número de Cutter | S966r |
xxxi, 453 pages : 23 cm