Formal specification and verification in VLSI designde Bruce S. Davie · Publicada por primera vez en 1990MateriasIntegrated circuitsVery large scale integrationComputer-aided designVerificationIntegrated circuits, very large scale integrationDesign and constructionTestingData processingEdiciones (1)Formal specification and verification in VLSI design (1990)
Formal Specification and Verification in VIsi Design (Edinburgh Information Tech (Edinburgh Information Technology Series, 8)1991