Minimization of multiple-valued programmable logic array using simulated annealing
Edición de la obra Minimization of multiple-valued programmable logic array using simulated annealing
| Autor | Robert C. Earle |
|---|---|
| Editorial | Naval Postgraduate School, Available from the National Technical Information Service |
| Fecha de publicación | 1991 |
| Lugar | Monterey, Calif, Springfield, Va |
| Idioma | inglés |
| Páginas | 58 |
| Número de Cutter | E12m |